Simulation and validation of diagram ladder petri nets

Abstract

Automated systems based on programmable logic controllers (PLC) are still applied in discrete event systems (DES) for controlling and monitoring of industriaprocesses signals. PLC-based control systems are characterized for having physical input and output signals coming from and going to sensors and actuators, respectively, whicthey are in direct contact with the production or manufacturing process. The input subsystem to PLC consists of sensor-wiring-physical inputs module, and it can present two kinds of faults: short circuit or open circuit, in one or more signals of the process physical inputs, which it causes faults in the control and/or in the control algorithms behavior. Ladder diagram (LD) is one of the five programminlanguages supported by the International Electrotechnical Commission (IEC) through the IEC-61131-3 standard, anit remains being used at industry for control algorithm design of PLC-based systems. This paper proposes the simulation and validation of control algorithms developed in LD by using Petri Nets (PN) in order to deal with the possible fault options (short circuit and/or open circuit) in the physical inputs subsystem of a PLC-based control system. One control algorithms in LD have been analyzed in order to show the advantages of the proposed approach.